Differences between BJT and FET (Bipolar Junction Transistor Vs Field Effect Transistor)

Structured Digital System Design (SDSD) - Syllabus

UNIT-I

Introduction, Concepts of digital design, the logic operators, Hardware Aspects related to asserted and not-asserted conditions, Mechanical switches for signal sources, Concept of inverter, General Implementation procedures, Arithmetic circuits, comparators, multiplexers, Code converters.

UNIT-II

Wired logic, Practical aspects of Wired logic and Bus-oriented Structures, Tristate Bus Systems, Practical aspects related to Combinational Logic Design, Fan-in Fan-out, Propagation Delay.

UNIT-III

Introduction Sequential Machine Design, The need for sequential Circuits, Basic Architectural Distinctions between Sequential machines, Fundamentals of Sequential Machine operation, clock and Oscillators, The design of a Clocked Flip-Flop, Flip-Flop conversion from one type to another, Practical clocking Aspects Concerning Flip-Flops, Timing and Triggering Considerations, Clock Skew.

UNIT-IV

Introduction Sequential Analysis and Design, The State Diagram, Analysis of Synchronous Sequential Circuits, A Synchronous Analysis Process, Approaches to the Design of Synchronous Sequential Finite State machines, Design steps For Traditional Synchronous sequential circuits, State Reduction, Minimizing the next door Decoders with JK or T Flip-Flop, Output Decoder Design.

UNIT-V

Counters, Design of Single Mode Counters, Design of Specialized Multi-mode Counters, Ripple Counters, Shift Register, Shift Registers and Memory.

UNIT-VI

Introduction Multi-Input System controller design, System Controllers, Controller Design Phases and System Documentation, Defining the purpose and Role of the system, Defining the Basic Operational Characteristic of the system, The controlling Systems and the controlled system, Timing and Frequency considerations, Functional Partition detailed Flow Diagram Development, System Controller state Specification(MDS diagram Generation),

UNIT-VII

Synchronizing two Systems and choosing Controller Architecture. The State Assignment, The next state decoder, Next State Decoder Maps, The output decoder, Clock Frequency Determination, Power Supply requirements, Control and Display, Concepts related to the use of conditional Outputs.

UNIT-VIII

Introduction, Using MSI decoder in System Controllers, Using MSI Multiplexers in System Controllers, System Controllers with more Complexity Indirect Addressed Multiplexers configuration, Read Only Memories, ROM’s , PROM’s and Applications, Using a PROM for Random Logic, Programmed Logic Arrays, Applications of PLA’s and FPLA’s.

TEXT BOOK:-

1.         An Engineering Approach to Digital Design – by William-I Fletcher, PHI  Pvt.  Ltd.

2.         Logic designs Theory – N.N. Biswas. PHI

REFERENCES:

       

1.     Digital Systems Testing & Testable Design – Miron Abramoviu, Melvin A. Breuer and Arthur D. Friedman

2.         Switching & Finite Automata Theory Z.Kohavi, @nd Edition. THi

3.         Digital Design Morris Mano-PHI, #rd Edition 2006.

4.         Digital Circuits & Logic Design-by Samuel C.Lee. PHI.

SDSD - I Mid Objective Paper with Answers (Feb 2013)

CVR College of Engineering

Autonomous - Affiliated to JNTUH

B.Tech. ­­_II­_ Year _II­_ Sem. – _I­_ MID, February – 2013

Subject: Digital System Design (Objective type Exam)

     Section – A : Multiple Choice Questions                   [ 10 x 1/2  = 5 marks ]

1.      In ______________________ system, HIGH voltage is modeled as logic 1 and

LOW voltage as logic 0.

a) Positive logic           b) Negative logic         c) Mixed logic             d) None

2.      Tristate Devices consists of __________ number of states.

a) 1                              b) 2                             c) 3                              d) 4

3.      A Gate whose output transfers to one of its two possible outputs when all of its inputs are brought to a common level and maintains this level only under this condition is said to exhibit ____________________ operation.

a) OR              b) AND                       c) XOR                       d) None

4.      A TTL NAND gate has output voltage parameters as V_OH= 2 volts and V_OL= 0.8 volts. If the output of NAND gate is at 3.2 volts, then HIGH level Noise Margin is _____________

a) 2 volts                      b) 1.8 volts                  c) 1.2 volts                     d) 3.2 volts

5.      TTL logic family has HIGH voltage range as 2 to 5 volts and LOW voltage range as 0 volts to 0.8 volts. If the output voltage is at 0.4 volts, then LOW level Noise Margin is ________

a) 0.2 volts                   b) 0.8 volts                  c) 1.2 volts                     d) 0.4 volts

    

                        
                                                   

7.      Minimum time required for the data to be stable , before the triggering edge is called as

a) Hold time                 b) Setup time               c) clock skew               d) propagation time

                                                  Ans (8) :  AND

                                                 Ans (9) :  5 KHz

10.  For JK flip flop, which of the following input is asynchronous input.

a) J                   b) K                 c) preset                       d) clock

Section – B : Fill up the blanks                                                            [10 x 1/2  = 5 marks]

1.      Difference between AND gate and AND operation is __________________

      

Ans : 

4.         The symbol and truth table for active LOW tri state inverter is _____________

                Ans :

5.      The excitation table for JK flip flop is _________
                Ans :

6.      Serial adder is a  Sequential circuit.

7.      Any gate which performs boolean AND operation can also perform Boolean OR operation.

8.      Output of Moore sequential circuit depends on only present state.

9.      Output of active LOW tristate buffer is High Impedance State (Z) , when enable is HIGH.

10.  In JK flip flop, if present state is ‘1’, and inputs applied as J = 0 and K = 0 then the output of JK flip flop is 1(Same as Present State).