SDSD - I Mid Objective Paper with Answers (Feb 2013)

CVR College of Engineering

Autonomous - Affiliated to JNTUH

B.Tech. ­­_II­_ Year _II­_ Sem. – _I­_ MID, February – 2013

Subject: Digital System Design (Objective type Exam)

     Section – A : Multiple Choice Questions                   [ 10 x 1/2  = 5 marks ]

1.      In ______________________ system, HIGH voltage is modeled as logic 1 and

LOW voltage as logic 0.

a) Positive logic           b) Negative logic         c) Mixed logic             d) None

2.      Tristate Devices consists of __________ number of states.

a) 1                              b) 2                             c) 3                              d) 4

3.      A Gate whose output transfers to one of its two possible outputs when all of its inputs are brought to a common level and maintains this level only under this condition is said to exhibit ____________________ operation.

a) OR              b) AND                       c) XOR                       d) None

4.      A TTL NAND gate has output voltage parameters as V_OH= 2 volts and V_OL= 0.8 volts. If the output of NAND gate is at 3.2 volts, then HIGH level Noise Margin is _____________

a) 2 volts                      b) 1.8 volts                  c) 1.2 volts                     d) 3.2 volts

5.      TTL logic family has HIGH voltage range as 2 to 5 volts and LOW voltage range as 0 volts to 0.8 volts. If the output voltage is at 0.4 volts, then LOW level Noise Margin is ________

a) 0.2 volts                   b) 0.8 volts                  c) 1.2 volts                     d) 0.4 volts

    

                        
                                                   

7.      Minimum time required for the data to be stable , before the triggering edge is called as

a) Hold time                 b) Setup time               c) clock skew               d) propagation time

                                                  Ans (8) :  AND

                                                 Ans (9) :  5 KHz

10.  For JK flip flop, which of the following input is asynchronous input.

a) J                   b) K                 c) preset                       d) clock

Section – B : Fill up the blanks                                                            [10 x 1/2  = 5 marks]

1.      Difference between AND gate and AND operation is __________________

      

Ans : 

4.         The symbol and truth table for active LOW tri state inverter is _____________

                Ans :

5.      The excitation table for JK flip flop is _________
                Ans :

6.      Serial adder is a  Sequential circuit.

7.      Any gate which performs boolean AND operation can also perform Boolean OR operation.

8.      Output of Moore sequential circuit depends on only present state.

9.      Output of active LOW tristate buffer is High Impedance State (Z) , when enable is HIGH.

10.  In JK flip flop, if present state is ‘1’, and inputs applied as J = 0 and K = 0 then the output of JK flip flop is 1(Same as Present State).