SDSD - I Mid Objective Paper with Answers (Jan 2011)

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY

 II B.Tech. II Sem., I Mid-Term Examinations, Jan/Feb– 2011

                                   STRUCTURED DIGITAL SYSTEM DESIGN

                                                                   

I 1.	Choose the correct alternative: The gate ideally suited for bit comparison is a		[	]
	a) Two-input XNOR gate         b) Two – input NOR gate c)  Two-input XOR gate          d) Two-input NAND gate
2	For checking of parity of a digital word , it is preferable to use a)AND gate            b)EX –OR gate              c) NAND    gate	d) NOR    gate	[	]
3	In a hexadecimal –to – binary priority encoder		[	]

a)O (hex ) has the highest priority                    b) F (hex) has the lowest priority

c) 7 (hex) has the lowest priority                       d) F (hex) has the highest priority

4          Wired logic is not possible in                                                                                    [           ]

a) ECL             b) open  collector TTL         c) TTL with active pull –up      d) TTL with passive pull –up

5          If a logic circuit has a fan – out of 4 , then the circuit                                                 [           ]

a) Has 4 inputs                                                             b) has 4 outputs

c) can drive a maximum of 4 inputs                              d) gives output 4 times the input

6          In a J-K Flip flop , when J=K=1 and clock is applied , the output Q will                   [           ]

a) Not change                           b) becomes 1

c) becomes 0                           d) be complement of the output before the clock is applied

7          In T flip –flop the output frequency is                                                                       [           ]

a) Same as input frequency                              b) double the input frequency  c) one-half its input frequency         d) none of above

8          Which indicates the next state in a state diagram ?                                                     [           ]

a) Circle      b) arrow tail             c)  arrow Head              d) none of above

9          A 4 – variable logic expression can be realised by using only one                               [           ]

a) NAND gate            b) demultiplexer                 c)  NOR   gate          d)  16:1 multiplexer

10        Which of the following logic families has the least propagation delay?                         [           ]

a) RTL               b) DTL                     c) DTL                     d) I2L

II        Fill in the blanks:

11        The special shortened format for all our signals is called Mnemonics.

12         Negative Logic is defined by logic variables or mnemonics that are Asserted for Logic LOW.

13        VEM stands for  Variable Entered Map (same as K- Map).

14        The 7442 BCD Decoder has active HIGH (LOW , HIGH) inputs and active

LOW  (LOW , HIGH) outputs.

15        The fan –in of a gate is equal to the number of  Identical Gates which are connected to it and used as inputs

16        The propagation delay time specified on the logic gate data sheets is usually the Average Of tPLH and  tPHL

17        A table showing present states , next states and conditions at flip – flops is called State Table.

18        A sequential circuit has Combinational Blocks and Flip Flops(Memory).

19        Blanking of zeros on the Left of the number is called leading zero suppression.

20       When subtracting hex digits , if least significant digit borrows from its left ,its value increases by

16.