SDSD - II Mid Objective Paper with Answers (April 2013)

CVR College of Engineering

II B.Tech. II Sem., II Mid-Term Examinations, April -2013

                                      STRUCTURED DIGITAL SYSTEM DESIGN

Answer All Questions. All Questions Carry Equal Marks.

I 1.	Choose the correct alternative: The type of register in which data is entered into it only one bit at a time , but has all data bits
	available as output is                                                                                                               [ a) SIPO           b) SISO            c) PISO          d) PIPO	]
2.	The number of states in a decade counter is                                                                           [ a) 5      b) 10                c) 15                d) 12	]
3.	The type of register in which we have access only to left most and right most flip flop is   [ a) SISO            b) shift left register                 c) PIPO           d) SIPO	]
4.	The capacity or size of a PLA is specified by the                                                                   [ a) Number of inputs       b) Number of product terms      c) Number of outputs       d) all of above	]
5.	A  PLA Consists of                                                                                                                [ a) AND Matrix            b) OR Matrix             c) Invert / Non invert matrix    d) all of above	]
6.	A universal shift register                                                                                                         [ a) accepts serial data                                       b) accepts parallel data c) gives serial and parallel output                    d) capable of all of above	]
7.	SYSTEM CONTROLLER is used for                                                                                   [ a)  Sequential circuits        b) Combinational circuits              c) PLA        d) PAL	]
8.	The resulting modulus of  cascading of Mod 5 and Mod 12 Counters  is                             [ a)  5                b)  12               c)  17               d)  60	]
9.	An action block in first cut flow diagram is equivalent to ………….. in a MDS diagram.  a)  Branch    b)  Input    c)  Output  d)  State                                                                       [	]
10.	Number of states in 4 bit ring counter is                                                                                [ a)  16               b)  8                 c) 4                         d) none of above	]

                                                                                                                 

II.       Fill in the blanks

11.    The number of unique states a counter can reside in generally referred to as its

Modulus.

12.       In Unit distance counters, there is only One bit (or One Flip-Flop) will change between consecutive states.

13.       Decoding logic for Mod 5 three bit UP counter using NAND gate is ……………………….

14.       The 5 bit Johnson Counter will have  …10…… number of unique states.

15.       System controller is a special Sequential Machine with more no.of Control inputs.

16.       The diamond is used to make Two (YES/NO) way decision.

17.       MDS stands for Mnemonic Documented State diagram.

18.       The  possible mnemonics for LOAD DATA and STORE DATA signals are LDATA and SDATA (LDA and SDA).

19.       The function of System Controller is to interpret system level control input sequences and in turn to generate system level outputs.

20.        P LA stands for Programmable Logic Array.