SDSD - II Mid Objective Paper with Answers (April 2011)

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD 

II B.Tech. II Sem., II Mid-Term Examinations, March/April -2011

STRUCTURED DIGITAL SYSTEM DESIGN

                                                                         Objective Exam

I 1.	Choose the correct alternative: The type of register in which data is entered into it only one bit at a time , but has all data bits
	available as output is S                                                                                                            [ a) SIPO            b) SISO            c) PISO          d) PIPO	]
2.	The number of stated in a decade counter is                                                                          [ a) 5       b) 10                c) 15                d) 12	]
3.	The type of register in which we have access only to left most and right most flip flop is   [ a) SISO            b) shift left register                 c) PIPO           d) SIPO	]
4.	The capacity or size of a PLA is specified by the                                                                   [ a) Number of inputs       b) number of product terms      c) number of outputs       d) all of above	]
5.	A PLA Consists of                                                                                                                 [ a) AND MATRIX        b) OR MATRIX        c) invert/non invert matrix        d) all of above	]
6.	A universal register                                                                                                                 [ a) Accepts serial data                                       b) accepts parallel data c) gives serial and parallel output                    d) capable of all of above	]
7.	SYSTEM CONTROLLER is used for                                                                                   [ a)  Sequentail circuits        b) combinational circuits              c) PLA        d) PAL	]
8.	Power supply requirement for system controller  is                                                                [ a)  5v              b) 10v              c) 20 v             d) 25 v	]
9.	If system controller is to see short input pulse (to avoid fault 1) following relation should hold  a)  tp > tc     b) tc >tp      c) tp=tc     d) none of above                                                          [	]
10.	IC NUMBER 74LS138 is used as                                                                                         [ a)  Flip flop      b) register        c) state decoder      d) none of above	]

II.       Fill in the blanks

11.    The number of unique states counters can be caused to reside in generally referred to as its

Modulo Number.

12.       In unit distance counters there is only ONE bit change per input change.

13.       Shift registers are classified by Single Mode & Multimode Specifications

14.       Parallel In-Parallel out is sometimes referred to as Broadside Load.

15.       System controller is a special Sequential Machine.

16.       The diamond is used to make Two (YES / NO)  Way  decision

17.       MDS stands for Mnemonic Documented State diagram.

18.       TAKE DATA and DATA TAKEN are Handshake signals

19.       System clock frequency is 1K Hz

20.        PLA stands for Programmable Logic Array.